Digital gain controller and gain control method

ABSTRACT

A current optimal gain can be calculated directly from an effective value of an input signal by increasing the speed of the initial response without using a feedback loop, in a manner such that a mean power of the input signal and the square-root of the mean power are calculated as an inverse of the effective value, and the input signal is multiplied by the product of this inverse of the number and predetermined effective value.

BACKGROUND OF THE INVENTION

The present invention relates to a digital gain controller and gaincontrol method in a modulator-demodulator (MODEM).

A signal processing section in a conventional MODEM which isstandardized by the CCITT recommendation V.29, V.27 ter is generallycomprised of a software of digital signal processor (DSP).

In general, a signal level which is inputted into a reception-side MODEMfrom a communication line differs every time of communication. Thesignal level needs to be amplified to be a constant level so thatprecision of a signal processing can be improved by efficientlyutilizing the limited dynamic range of the DSP. Otherwise, the dataerror rate is increased due to the low precision of the signalprocessing.

Therefore, an automatic gain controller (AGC) adjusting an amplifyinggain is internally placed in the MODEM in response to a reception signallevel.

In the MODEM V.29, V.27 ter, a training signal sequence is transmittedprior to a data transmission for initializing each signal processor inthe reception-side MODEM. The PN segment in this training signalsequence is a signal for initializing an adaptive equalizer. If the PNsegment is not correctly demodulated, the initialization cannot beprocessed. Therefore, a correctly demodulated signal needs to beobtained in a manner such that initializations for the signal processorsexcept for the equalizer are completed prior to the PN segment. For thisreason, the AGC gain must be converged before the PN segment. That is,an AGC having quick initial response is required.

However, efficiency of the DSP has been improved recently and the bitlength of a signal to be processed and operation speed are bothincreased. Therefore, the signal processing which was conventionallyperformed outside of the DSP because of the precision of the signalprocessing to be obtained and the limitation of operation time to bespent can now be executed inside of the DSP. In the case of the AGC, ananalog type AGC circuit has been conventionally arranged outside of theDSP, however, a digital type AGC generally comprises the DSP software atpresent.

FIG. 13 is a block diagram illustrating the structure of theconventional feedback type digital AGC. The character δ is a positiveconstant, P₀ is a predetermined power, and r₀ (n), r₀ '(n), P₀ (n), e₀(n), g₀ (n) are signal values at each section (which will be describedlater) at the sampling time n, which respectively represent an inputsignal, output signal, mean power signal of output, error signal, andgain signal.

In FIG. 13, the gain signal g₀ (n-1) which has been decided in onesampling earlier than n and stored in the delay 22 is multiplied by theinput signal r₀ (n). The output signal r₀ '(n) is obtained by:

    r.sub.0 '(n)=g.sub.0 (n-1)·r.sub.0 (n)            (1)

Then, this output signal r₀ '(n) is squared by the multiplier 27 andaveraged by the low pass filter (LPF) 26. The mean power signal P₀ (n)is obtained by:

    P.sub.0 (n)=E(r.sub.0 '(n).sup.2)                          (2)

The "E" represents "mean".

Then, an error signal e₀ (n) of the above-mentioned mean power signal P₀(n) and the predetermined power P₀ is calculated in the power errorcalculator 25 by:

    e.sub.0 (n)=P.sub.0 -P.sub.0 (n)                           (3)

As apparent from the above equation (3), in the case where the meanpower of the output signal r₀ '(n) is greater than the predeterminedpower, the error signal e₀ (n) becomes negative, while in the case wherethe mean power is smaller than the predetermined power, it becomespositive. Then, the error signal e₀ (n) is multiplied by a constant inthe constant multiplier 24, and a cumulative addition is performed bythe adder 23 and delay 22.

The gain signal which is stored in the delay 22 is obtained as thefollowing and used as a gain at the sampling time n+1:

    g.sub.0 (n)=g.sub.0 (n-1)+δ·e.sub.0 (n)=g.sub.0 (n-1)+δ[P.sub.0 -P.sub.0 (n)]                       (4)

As apparent from the equation (4), in the conventional AGC circuit, inthe case where the mean power P₀ (n) of the output signal is greaterthan the predetermined power P₀, a gain is decreased. While in the casewhere the mean power P₀ (n) is smaller than the predetermined power P₀,a gain is increased. That is, in the AGC method, the algorithm whichsequentially corrects a gain so that the error e₀ (n) of the mean powerP₀ (n) of the output signal and predetermined power P₀ approaches tozero is directed. If a value of the positive constant δ is appropriatelyselected, the mean power P₀ (n) of the output signal is eventuallyconverged into the predetermined power P₀ by repeating this operation.

Since it is apparent from the equation (3) that e₀ (n)=0, and from theequation (4), g₀ (n)=g₀ (n-1), the gain is converged into a certainvalue.

The traceability of the AGC gain has a relation with the positiveconstant δ. That is, a change of the gain for an operation is obtainedfrom the equation (4) as the following:

    |g.sub.0 (n)-g.sub.0 (n-1)|=δ|e.sub.0 (n)|                                             (5)

Therefore, if δ is set to a large value, the change of the gain isincreased, and the traceability of the gain is quickened.

As described above, the characteristics that an initial response is asquick as possible and the gain is not fluctuated after the PN segment sothat the correctly demodulated signal can be obtained are required forthe AGC. Therefore, in general, the speed of the traceability before thePN segment is increased by changing the positive constant δ, and thespeed of traceability after the PN segment is decreased.

However, in the aforementioned conventional feedback type digital AGC,if the constant δ is increased to increase the speed of thetraceability, large fluctuation is caused because the gain changebecomes susceptible. In the worst case, the gain is diverged. That is,the conventional feedback type digital AGC has the limitation toincrease the speed of the initial response since the gain issequentially corrected.

Therefore, in the case where a signal level is quite large, the drawbackis that the convergence of the gain cannot be completed before the PNsegment and the adaptive equalizer cannot be initialized correctly.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide adigital gain controller and gain control method which calculates acurrent optimal gain obtained directly from the effective value of aninput signal by increasing an initial response without using a feedbackloop.

According to the present invention, the foregoing object is attained byproviding a digital gain controller comprising: operation means forcalculating the inverse of an effective value of an input signal; firstsignal generation means for generating a gain signal in a manner suchthat the inverse of the effective value is multiplied by a predeterminedeffective value; and second signal generation means for generating anoutput signal in a manner such that the input signal is multiplied bythe gain signal.

It is another object of the present invention to provide a digital gaincontroller capable of converging a gain before a PN segment regardlessof reception signal level.

According to the present invention, the foregoing object is attained byproviding a digital gain controller comprising: operation means forcalculating a mean amplification of an input signal; first gaincontroller for generating an amplification signal which is proportionalto the input signal having one-fourth of the ratio of the effectivevalue of the input signal to the mean amplification based on the inputsignal as an effective value; and second gain controller for generatingan output signal which is proportional to the amplification signalhaving an effective value which is equal to the predetermined effectivevalue.

Other features and advantages of the present invention will be apparentfrom the following description taken in conjunction with theaccompanying drawings, in which like reference characters designate thesame or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explaining a signal processing in the digitalgain controller according to the first embodiment in the presentinvention;

FIGS. 2A-2B is a flowchart illustrating the internal processing in theoperation apparatus according to the first embodiment;

FIG. 3 is a diagram illustrating the structure of the register accordingto the first embodiment;

FIG. 4 is a diagram illustrating the structure of the register accordingto the modified embodiment of the first embodiment;

FIG. 5 is a diagram illustrating the structure of the digital automaticgain controller according to the second embodiment;

FIG. 6 is a diagram illustrating the fixed point format of the DSP whichis used in the second embodiment;

FIG. 7 is a flowchart illustrating the internal processing in themultiplier 33 according to the second embodiment;

FIG. 8 is a block diagram illustrating the structure of the multiplier35 according to the second embodiment;

FIG. 9 is a flowchart illustrating the processing in the operationapparatus 34 according to the second embodiment;

FIG. 10 is a block diagram illustrating the structure of the digitalautomatic controller according to the third embodiment of the presentinvention;

FIG. 11 is a diagram illustrating the fixed point format of the DSPaccording to the third embodiment;

FIG. 12 is a diagram for explaining a signal processing inside of themultiplier 313 according to the third embodiment; and

FIG. 13 is a block diagram illustrating the structure of theconventional feedback type digital AGC.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will now be described indetail in accordance with the accompanying drawings.

First Embodiment

FIG. 1 illustrates a signal processing in the digital gain controller(which is referred to as a "controller" thereinafter) according to thefirst embodiment in the present invention. As shown in the diagram, thepresent controller is comprised of the multiplier 11, low pass filter(LPF) 12, operation apparatus 13 which calculates the inversesquare-root of x for an arbitrary positive number x, constant multiplier14, and multiplier 15. In the diagram, V₀ is a predetermined effectivevalue, and r(n), r'(n), Pi(n), g(n) are signal values in each portion ofthe controller at the sampling time n, which respectively represent aninput signal, output signal, mean power signal of input, and gainsignal. Furthermore, the present controller is comprised of the softwareof the floating point type DSP for the signal processing.

The mean power signal P_(i) (n) is obtained in a manner such that theinput signal r(n) is squared by the multiplier 11 and averaged by theLPF 12. That is:

    P.sub.i (n)=E(r(n).sup.2)                                  (6)

Then, the mean power signal P_(i) (n) is inputted into the operationapparatus 13 and P_(i) (n)^(-1/2) is calculated. The value P_(i)(n)^(-1/2) which is outputted from the operation apparatus 13 ismultiplied by the predetermined effective value V₀ in the constantmultiplier 14, and the gain signal g(n) is obtained by: ##EQU1## Thedenominator of the above equation (7), the square root of E(r(n)²),represents an effective value of the input signal r(n).

The output signal r'(n) is obtained in a manner such that the gainsignal g(n) is multiplied by the input signal r(n) in the multiplier 15.That is: ##EQU2##

By the equation (8), the effective value of the output signal r'(n) is:##EQU3## It is apparent from the above equation that the effective valueof the output signal is equal to the predetermined effective value V₀.

Accompanying with the flowcharts in FIGS. 2A and 2B, the internalprocessing in the operation apparatus 13 according to the presentembodiment is described in detail. In the same flowcharts, a, b, c, d,de, and df respectively represent values inputted in the registers a, b,c, d, de, and df. As shown in FIG. 3, the register d is comprised of thesign bit S, M-bit exponent de, and N-bit mantissa df. The register derepresents integers 0˜(2^(M) -1) and the register df represents decimals0˜(1-2^(-N)). These registers can be processed as independent registers.

In the DSP used in the controller according to the present embodiment,the following relation is formed:

    d=(-1).sup.S ×(1+df)×2.sup.de-K                (10)

where K represents a constant integer in 0˜(2^(M) -1). In addition, thestructure of the register is similar to that of the register shown inFIG. 3, and the relation indicated in the equation (10) can be alsoformed on the registers a and b.

First, an input signal to the operation apparatus 13 is inputted intothe register d. The value of the input signal at this time is set to asthe following:

    d.sub.0 =(-1).sup.0 ×(1+df.sub.0)×2.sup.de0.sub.-K (11)

The principal of the operation apparatus 13 is to multiply theinverse-square root of the mantissa (1+df₀) by the inverse-square rootof the exponent 2^(de0) _(-K). In the procedure of processings whichwill be described below, steps S2-S9 are the operations for the mantissaand other steps are for the exponent.

In FIG. 2A, in step S1, as a preparation for the operations for theexponent after step S10, de=de₀ is saved in the address M0 in thememory. Then, in step S2, the constant integer K is inputted into theregister de. If d is determined as d₂ at this time, only the mantissa isappeared as the following:

    d.sub.2 =(1+df.sub.0)×2.sup.K-K =(1+df.sub.0)        (12)

For df₀ and d₂, the following relations are formed:

    0≦df.sub.0 ≦(1-2.sup.-N)                     (13)

    1≦d.sub.2 ≦(2-2.sup.-N)                      (14)

Therefore, the mantissa is d₂ ^(-1/2), the inverse-square root of d₂which is in the range of 1˜2. To obtain d₂ ^(-1/2), an approximate valueof d₂ ^(-1/2) is calculated by the approximate polynomial. The obtainedvalue is determined as an initial value and converged into a true valueby the iterative method.

In step S3, d=d₂ is saved in the register a for later processings. Instep 4, the approximate value f(d₂) of d₂ ^(-1/2) is calculated by thefollowing approximate polynomial and the result is inputted into theregister d:

    f(x)≈x.sup.-1/2 (1≦x≦2)              (15)

In this process, the value in the register a needs to be kept.

If the value d at the completion of step S4 is determined as d₄, thefollowing equation is obtained:

    d.sub.4 =f(d.sub.2)≈d.sub.2.sup.-1/2               (16)

From the view of the amount of operation, a desirable approximatepolynomial used here is one in which the order is as low as possiblehaving an efficient approximate precision. For this reason, acoefficient of the polynomial f(x) is determined so that f(x) becomes aChebyshev approximation of x^(-1/2). As more particularly describing, acoefficient of the polynomial f(x) of p-th order is determined so as tominimize the following: ##EQU4##

In steps S5-S8, d4≈d₂ ^(-1/2) is determined as an initial value and atrue value of d₂ ^(-1/2) is calculated by the iterative method. That is,in step S5, a number of occurrence R is inputted into the repeat counterC, and in step S6, the value d is renewed by the two-variable functiong(x, y). Again, the value in the register a needs to be kept here.

Furthermore, the function g(x, y) is determined so that the series{X_(n) } which is defined by the following recursion formula (18) is tobe as the following equation (19): ##EQU5##

In steps S7 and S8, in the case where the value of the repeat counter Cis not 1, decrement is performed and the process returns to step S6.Since when the processing enters to this processing loop, a=d₂, d=d₄ ≈d₂^(-1/2), if the value d is repeatedly renewed in step S6 (that is, g(d,a)→d), the value d approaches to a^(-1/2) =d₂ ^(-1/2).

Since when the processing in step S6 is iterated for R times, the valueof the repeat counter C becomes to 1 and the processing gets out of theaforementioned processing loop. The value d at this time is determinedas d₈.

If the number of occurrence R is selected so that an error |d₈ -d₂^(-1/2) | at the completion of iteration is less than a numericprecision of the DSP, d₈ can be regarded as a true value of d₂ ^(-1/2).Therefore, from the equation (12), the following equation is obtained:

    d.sub.8 =d.sub.2.sup.-1/2 =(1+df.sub.0).sup.-1/2           (20)

In this way, the inverse square-root of the exponent of d₀ is obtained.

In step S9 in FIG. 2B, d=d₈ is saved in the register a for laterprocessings. In step S10, de=de₀ which was saved in the address M0 instep S1 is returned to the register de and the NOT (inverse) operationis performed. This value is again saved in the address M0. At this time,the value of the address M0 is as the following:

    (M0)=de.sub.0 =(2.sup.M -1)-de.sub.0                       (21)

In step S11, by using de=de₀ , the following is calculated and theresult is inputted into the register b: ##EQU6## The [X] represents amaximum integer which is less than x. In step S11, the value in theregister a needs to be kept. Furthermore, the value b at the completionof the processing in step S11 is: ##EQU7##

In step S12, a=d₈ which was saved in step S9 is multiplied by the valueb which was calculated in step S11, and the result is inputted into theregister a. In this case, from the equations (20) and (22), thefollowing equation is obtained: ##EQU8## In step S13, de=de₀ which hasbeen saved in the address M0 in step S10 is returned to the register deand multiplied by 1/2. Thus, the integer [de₀ /2] can be obtained.Furthermore, the register df is cleared.

If the value d at this time is determined as d₁₃, the following equationis formed: ##EQU9##

In step S14, the value a obtained in step S12 is multiplied by the valued obtained in step S13, and the result is inputted into the register d.If the value d at this time is determined as d₁₄, the following equationis obtained from the equations (23) and (24): ##EQU10## If the equation(21) is substituted in the equation (25), the following equation isobtained:

    d.sub.14 =(1+df.sub.0).sup.-1/2 ×(2.sup.de0-K).sup.-1/2(26)

Thus, the inverse-square root of the exponent is obtained. If theequation (11) is used, the following equation can be obtained:

    d.sub.14 ={(1+df.sub.0)×2.sup.de0.sub.-K)}.sup.-1/2 =d.sub.0.sup.-1/2(27)

Thus, the value d at the completion of the processing in FIG. 2B is theinverse square-root of d at the beginning of the processing.

In this way, the operation apparatus 13 is comprised of the software ofthe floating point type DSP.

As described above, an optimum gain can be obtained directly from theeffective value of the input signal in the digital gain controllerwithout using the feedback loop in a manner such that the inverse of theeffective value of the input signal is calculated, and is multiplied bythe predetermined effective value, which is a gain.

In the controller according to the present embodiment, since the initialresponse is quickened in comparison with that of the feedback type AGC,the gain can be converged before the PN segment regardless of the signallevel.

Then, the modified embodiment of the first embodiment is described.

Modification

The structure of the register d of the DSP according to the modifiedembodiment is shown in FIG. 4. The register d is comprised of the M-bitexponent de and the N-bit mantissa df, and the following relation isformed:

    d={(-1).sup.S ×1/2+df}×2.sup.de                (10-1)

The "S" in the mantissa is a sign bit, and the formats for de and df areboth complements of 2. The "de" represents integers in -2^(M-1) ˜2^(M-1)-1, and "df" represents decimals in -2⁻¹ ˜2⁻¹ -2^(-N).

Furthermore, the input signal value to the operation apparatus 13 isdetermined as the following:

    d.sub.0 =(1/2+df.sub.0)×2.sup.de0 (d.sub.0 ≧0) (11-1)

The principle of the operation apparatus 13 is that the inversesquare-root of the mantissa (1/2+df₀) is multiplied by the inversesquare-root of the exponent 2^(de0).

In the procedure of the processings according to the modifiedembodiment, when the register de is cleared in the processing in stepS2A, the value d₂ is as following:

    d.sub.2 =(1/2+df.sub.0)×2.sup.0 =1/2+df.sub.0        (12-1)

Since the input signal d₀ is over 0, the following relations are formed:

    0≦df.sub.0 ≧2.sup.-1 -2.sup.-N               (13-1)

    2.sup.-1 ≦d.sub.2 ≦1-2.sup.-N                (14-1)

The mantissa is the inverse square-root of d₂ in the range of 2⁻¹ ˜1.

Therefore, as an approximate polynomial, the following is used:

    f(x)≈x.sup.-1/2  (2.sup.-1 ≦x≦1)     (15-1)

The approximate value f(d₂) of d₂ ^(-1/2) is calculated by the aboveinequalities, and the result is inputted into the register d. Thepolynomial f(x) is a polynomial of the p-th order to the fixed p havinga coefficient such that the following inequalities to be the minimumvalue: ##EQU11##

By repeating the renewal of the value d in steps S6-S8 in FIG. 2A, thevalue d₈, which is the value d when the processing gets out of the loopis:

    d.sub.8 =d.sub.2.sup.-1/2 =(1/2+df.sub.0).sup.-1/2         (20-1)

Thus, the inverse square-root of the mantissa of d₀ can be obtained.

In the processing corresponding to that of step S11 in FIG. 2B in themodified embodiment, the following can is calculated by using de=de₀ :

    2.sup.{3/2+(de/2-[de/2])}                                  (21-2)

The result is inputted into the register b. Therefore, the value b atthe completion of this processing is:

    b=2.sup.{3/2+(de0/2-[de0 .sub./2])}                        (22-1)

Furthermore, in step S12, the following equation is obtained from theequations (20-1) and (22-1): ##EQU12## In the modified embodiment, thevalue d, that is, the value d₁₃ at the completion of step S13 is:

    d.sub.13 =(1/2+0)×2.sup.[de0/2] =2.sup.[de0/2]-1     (24-1)

When the obtained value a is multiplied by d=d₁₃, the value d, that is,d₁₄ is as the following from the equations (23-1) and (24-1): ##EQU13##Since de₀ +1=-de₀, the value d₁₄ is obtained as following:

    d.sub.14 =(1/2+df.sub.0).sup.-1/2 ×(2.sup.de0).sup.-1/2(26-1)

In this way, the inverse square-root of the exponent can be obtained.Furthermore, from the equation (11-1), the following equation isobtained:

    d.sub.14 ={(1/2+df.sub.0)×2.sup.de0 }.sup.-1/2 =d.sub.0.sup.-1/2(27-1)

Therefore, the value d after the completion of the processing is theinverse square-root of d which is at the beginning of the processing.

Second Embodiment

The second embodiment according to the present invention is describedbelow.

FIG. 5 illustrates the structure of the digital automatic gaincontroller (which is referred to as a "controller" thereinafter)according to the second embodiment. The controller shown in FIG. 5 iscomprised of the multiplier 31, low pass filter (LPF) 32, multiplier 33multiplying by 2^(n) operation apparatus 34 calculating x^(-1/2) for1/2≦x<1, multiplier 35 multiplying by the value in which the absolutevalue is larger than or equal to 1, multiplier 36 multiplying by thevalue in which the absolute value is less than 1, and constantmultipliers 37 and 38. V₀ is a predetermined effective value.

Furthermore, r₂ (n), r₂ '(n), s₂ (n), t₂ (n), P_(i2) (n), q₂ (n), andK(n) are signal values at each portion of the controller at the samplingtime n. Among those, K(n) is an integer and the other values aredecimals in which the absolute values are less than 1. The controllershown in FIG. 5 is comprised of the software of the fixed point DSP.

FIG. 6 is a fixed point format of the DSP according to the presentembodiment. In the diagram, the character S, black dot, and character Nrespectively represent a sign bit, decimal, and total bit. Furthermore,the character M represents the total bit of the input signal r₂ (n) andinputted into the upper M bit. However, (M-1)×2≦N-1 needs to besatisfied.

In the controller shown in FIG. 5, the input signal r₂ (n) is squared bythe multiplier 31 and averaged by the LPF 32. The mean power signalP_(i2) can be obtained by:

    P.sub.i2 (n)=E(r.sub.2 (n).sup.2)                          (28)

Then, in the multiplier 33, the mean power signal P_(i2) is multipliedby 2^(K)(n)-1 while the following is calculated:

    K(n)=-[log.sub.2 P.sub.i2 (n)]                             (29)

In this way, the normalized power signal q₂ is obtained. However, [x]represents a maximum integer which is less than x. The multiplier 33outputs q₂ (n) and K(n) to the operation apparatus 34 and multiplier 35respectively.

From the equation (29), q₂ (n) is obtained by: ##EQU14## Since

    -1≦log.sub.2 P.sub.i2 (n)-[log.sub.2 P.sub.i2 (n)]-1<0 (30-1)

the normalized power signal q₂ (n) satisfies the following:

    2.sup.-1 ≦q.sub.2 (n)<1                             (30-2)

In the operation apparatus 34, the gain correction signal (1/2)q₂(n)^(-1/2) is calculated. In the multiplier 35, the input signal r₂ (n)is amplified based on K(n) which is inputted from the multiplier 33, andthe amplification signal s₂ (n) is obtained by:

    S.sub.2 (n)=r.sub.2 (n)×2.sup.(k(n)-5)/2             (31)

The amplification signal S₂ (n) is multiplied by the gain correctionsignal (1/2)q₂ (n)^(-1/2) in the multiplier 36, and the value t₂ isobtained. By using the equations (30) and (31), the value t₂ (n) can beobtained by: ##EQU15##

Furthermore, t₂ (n) is multiplied by the predetermined effective valueV₀ and 8 by the constant multipliers 37 and 38. The output signal r₂'(n) is obtained by: ##EQU16## Therefore, the gain is: ##EQU17##

By the way, in the case where the mean power signal P_(i2) (n) isconstant, the effective value of the output signal r₂ '(n) is is givenfrom the equations (28) and (33): ##EQU18## Thus, the effective value ofthe output signal r₂ '(n) is equal to the predetermined effective valueV₀.

Then, the internal processing in the multiplier 33 is described alongwith the flowchart in FIG. 7. In step S21, the mean power signal P_(i2)(n) which is an input signal to the multiplier 33 is inputted into theregister d of the DSP. Then, in step S22, the integer 1 is inputted tothe register l.

In step S23, the process is branched off based on the value of theregister d. In the case where 1/2≦d<1, the process proceeds to step S27.In other cases, the process proceeds to step S24 where the process isbranched off based on the value in the register 1. The value in theregister l is regarded as an integer, and if it is larger than 2M-2, theprocess proceeds to step S26. If not, the process proceeds to step S25.

In step S25, the value in the register d is doubled and the value of theregister l is increased by 1 when the value of the register l isregarded as an integer. That is, the steps S23, S24, and S25 arerepeated until 1/2≦d<1 or 1 ≧2M-2 is formed.

If the values of the register d and l in the processing at the j-th timeto the processing in step S23 are determined as d_(j) and l_(j)respectively, it is apparent from the flowchart shown in FIG. 7 thatd_(j) is a geometrical progression in which the first term is P_(i2) (n)and common ratio is 2. That is:

    d.sub.j =P.sub.i2 (n) 2.sup.j-1 (j≧1)               (36)

Furthermore, l_(j) is an arithmetical progression in which the firstterm is 1 and common difference is 1. That is:

    l.sub.j =1+(j-1)×1=j (j≧1)                    (37)

From the above equations (36) and (37), the following equation isformed:

    d.sub.j =P.sub.i2 (n) 2.sup.lj-1                           (38)

That is, if the values d and l for the processing to step S23 arerespectively determined as d_(A) and d_(B), the following relation isformed:

    d.sub.A =P.sub.i2 (n) 2.sup.l.sbsp.A.sup.-1 =2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+l.sbsp.A.sup.-1} (39)

When the processing gets out of the loop of steps S23-S25, there are twoways. One is that the processing passes through step S26 (passingthrough D in the flowchart) and the other is the process does not passthrough step S26 (passing through B). If the values d and l when theprocessing is passing through A and B are determined as d_(B) and l_(B)respectively, since there is no difference between the value d passing Aand the value l passing B, the following equation is formed as theequation (39):

    d.sub.B =P.sub.i2 (n) 2.sup.l.sbsp.B.sup.-1 =2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+l.sbsp.B.sup.-1} (40)

Furthermore, it is apparent from the flowchart that the followingrelation is formed:

    1/2≦d.sub.B <1                                      (41)

Therefore, from the equation (40), the following relation is furtherformed: ##EQU19## That is:

    -1≦log.sub.2 P.sub.i2 (n)+l.sub.B -1<0              (42-1)

    ∴-l.sub.B ≦log.sub.2 P.sub.i2 (n)<-(l.sub.B -1) (42-2)

Since -l_(B) is a maximum integer which is less than log₂ P_(i2) (n), itis expressed as the following:

    -l.sub.B =[log.sub.2 P.sub.i2 (n)]                         (43)

Therefore, from the equations (29) and (43), l_(B) is obtained by:

    l.sub.B =-[log.sub.2 P.sub.i2 (n)]=K(n)                    (44)

Furthermore, if the equation (44) is substituted in the equation (40),the following equation can be obtained from the equation (30):

    d.sub.B =P.sub.i2 (n).sup.K(n)-1 =q.sub.2 (n)              (45)

Therefore, the values d and l in the output B can be outputted as q₂ (n)and K(n).

On the other hand, from the equation (42-2), the following relation isformed:

    2.sup.-lB ≦P.sub.i2 (n)                             (46)

At the same time, from the flowchart, the following relation is formed:

    l.sub.B ≦2M-2                                       (47-1)

    ∴2.sup.-lB ≧2.sup.-2(M-1)                   (47-2)

Therefore, from the equations (46) and (47-2), in the case where theprocessing passes through B, the following relation is formed:

    P.sub.i2 (n)≧2.sup.-2(M-1)                          (48-1)

That is:

    Passing through B→P.sub.i2 (n)≧2.sup.-2(M-1) (48-2)

The pair of this condition is:

    P.sub.i2 (n)<2.sup.-2(M-1) →Not passing through B   (48-3)

Furthermore, since it is obvious that the loop of steps S23-S25 is notan infinite loop, the processing always passes either the process B orD. Therefore, the following conditions (49) and (50) are formed:

    Not passing through B⃡Passing through D        (49)

    Not passing through D⃡Passing through B        (50)

Therefore, the following relation is formed:

    P.sub.i2 (n)<2.sup.-2(M-1) →Passing through D       (51)

By the way, in the case where 1>2M-2 is formed when 1/2≦d<1 has notformed yet in the loop, the process branches into D and gets out of thisloop. If the values d and l at this time are respectively determined asd_(D) and l_(D), since d_(A) =d_(D), l_(A) =l_(D) according to theflowchart, the following relation is formed such as the equation (39):

    d.sub.D =P.sub.i2 (n) 2.sup.l.sbsp.D.sup.-1 =2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+1.sbsp.D.sup.-1} (52)

Furthermore, from that in the case where the determination in step S23is NO and the determination in step S24 is YES, the process branchesinto step S26, and that d<1 from the fixed point format, the followingrelations are formed:

    d.sub.D <1/2                                               (53)

    l.sub.D =2M-2                                              (54)

Therefore, from the equations (52), (53), and (54), in the case wherethe processing passes through D, the following relations are formed:

    2.sup.{log.sbsp.2.sup.P.sbsp.i2.sup.(n)+2M-3} <1/2         (55)

    P.sub.i2 (n)×2.sup.2M-3 <2.sup.-1                    (55-1)

    ∴P.sub.i2 (n)<2.sup.-2(M-1)                        (55-2)

That is:

    Passing through D→P.sub.i2 (n)<2.sup.-2(M-1)        (56)

If the pair of this condition is obtained and the equation (50) is used,the following relation is formed:

    P.sub.i2 (n)≧2.sup.-2(M-1) ⃡Passing through B (57)

At last, from the equations (48-2) and (57), the following condition isobtained:

    P.sub.i2 (n)≧2.sup.-2(M-1) ⃡Passing through B (58)

Furthermore, from the equations (51) and (56), the following conditionis obtained:

    P.sub.i2 (n)<2.sup.-2(M-1) ⃡Passing through D  (59)

According to the equation (59), in the case where the processing passesD, the effective value of the input signal r₂ (n) satisfies thefollowing: ##EQU20## Since the input signal r₂ (n) is a decimal in M bitincluding a sign, in the case where the equation (60) is satisfied, theinput signal is regarded as 0. At this time, if the definitions of theequations (29) and (30) are directed, K(n) becomes indefinite and q₂ (n)is not determined.

However, since the actual apparatus can express the only definite anddetermined values, in the case where the processing passes D, thefollowing values are outputted:

    q.sub.2 (n)=1/2                                            (61)

    K(n)=2M-2                                                  (62)

In the case where the processing passes D, since 1=2M-2, 1/2 is inputtedinto the register d in step S26 and the process branches into step S27,the values q₂ (n) and K(n) which satisfy the equations (61) and (62) areoutputted.

By the way, outputting the values q₂ (n) and K(n) corresponds to thatthe mean power P_(i2) (n) of the input signal is regarded as thefollowing from the equation (30):

    P.sub.i2 (n)=q.sub.2 (n)×2.sup.-K(n)+1 =1/2×2.sup.-(2M-2)+1 =2.sup.-2(M-1)                                            (63)

As apparent from the equations (58) and (59), the value P_(i2)(n)=2⁻²(M-1) is a border value between the case passing through B andthe case passing through D.

That is, in the case where the processing passes D, the mean powerP_(i2) (n) of the input signal should be regarded as 0. However, in theactual apparatus, it is regarded that the minimum P_(i2) (n) which canpass through B is inputted, and the values q₂ (n) and K(n) areoutputted.

In this way, the definite and determined q₂ (n), K(n) can be outputtedwith respect to an arbitrary P_(i2) (n).

Then, the detailed structure of the multiplier 35 is described.

FIG. 8 is a block diagram illustrating the structure of the multiplier35. As shown in the diagram, the multiplier 35 is comprised of theconstant multiplier 50, multiplier 51 multiplying by 2^(n), multiplier52 multiplying by a number in which the absolute value is less than 1,adder 53, operation apparatus 54 calculating the fixed point value2.sup.(L/2-[L/2]) -1 for the inputted integer L, and constant subtracter55. Furthermore, r₂ (n), x(n), s₂ (n), K(n), L(n), u(n), v(n), and a(n)are signal values at each portion of the multiplier at the sampling timen. Among those, the values except K(n) and L(n) are decimals in whichthe absolute values are less than 1. The present controller is alsocomprised of the fixed point DSP.

In FIG. 8, the input signal r₂ (n) is multiplied by 1/2 by the constantmultiplier 50 and x(n)=(1/2)r₂ (n) is obtained. In the constantsubtracter 55, L(n)=K(n)-3 is calculated based on the value K(n) whichis inputted from the multiplier 33 shown in FIG. 5. Furthermore, x(n) ismultiplied by 2.sup.[L(n)/2] in the multiplier 51 by using L(n), andu(n) is obtained as the following:

    u(n)=x(n)×2.sup.[L(n)/2] =(1/2)r.sub.2 (n)×2.sup.[(K(n)-3)/2](64)

Furthermore, in the operation apparatus 54, the fixed point value v(n)is calculated from the integer L(n)=K(n)-3, and the value v(n) is:

    v(n)=2.sup.((K(n)-3)/2-[(K(n)-3)/2]) -1                    (65)

Furthermore, in the multiplier 52, u(n) is multiplied by v(n), and thevalue a (n) is obtained. Then, a (n) and u(n) are added, and the values₂ (n) is obtained. That is, from the equations (64) and (65), thefollowing equations are obtained: ##EQU21##

Therefore, the multiplier 35 in FIG. 5 which has shown in FIG. 8calculates s₂ (n) of the equation (31) from the values r₂ (n) and K(n).

Then, the internal processing in the operation apparatus 34 isdescribed.

FIG. 9 is a flowchart illustrating a detailed processing in theoperation apparatus 34. In step S31, the input signal q₂ (n) to theoperation apparatus 34 is inputted into the register d of the DSP. Ifthe value in the register d at this time is determined as d₁, d₁ =q₂(n), and from the equation (30-2), the following relation is formed:

    1/2≦d.sub.1 <1                                      (68)

In order to obtain (1/2)d₁ ^(-1/2) for d₁ in this range, an approximatevalue of (1/2)d₁ ^(-1/2) is calculated by the approximate polynomial.The obtained value is set to as an initial value and converged to a truevalue by the iterative method.

In step S32, d=d₁ is saved in the register a for the later processings.Then, in step S33, the approximate value f(d₁) of (1/2)d₁ ^(-1/2) iscalculated by using the following polynomial:

    f(x)≈(1/2) x.sup.-1/2  (1/2≦x≦1)     (69)

The calculated value is inputted into the register d and the value inthe register a needs to be kept.

If the value d at the completion of the processing in step S33 isdetermined as d₃, the value d₃ is:

    d.sub.3 =f(d.sub.1)≈(1/2) d.sub.1.sup.-1/2         (70)

From the view of the amount of operation, a desirable approximatepolynomial used here is one in which the order is as low as possiblehaving an efficient approximate precision. For this reason, acoefficient of the polynomial f(x) is determined so that f(x) becomes aChebyshev approximation of (1/2)x^(-1/2). As more particularlydescribing, a coefficient of the polynomial f(x) of p-th order isdetermined so as the following to be minimum:

    max|f(x)-(1/2)x.sup.-1/2 | 1/2≦x≦2 (71)

In steps S34-S37, d₃ ≈(1/2)d₁ ^(-1/2) is determined as an initial valueand a true value of (1/2)d₂ ^(-1/2) is calculated by the iterativemethod. That is, in step S34, a number of occurrence R is inputted intothe repeat counter C, and in step S35, the value d is renewed by thetwo-variable function g(x, y). Again, the value a needs to be kept here.

Furthermore, the function g(x, y) is determined so that the series{X_(n) } which is defined by the following recursion formula (72) is tobe as the following equation (73): ##EQU22##

In steps S36 and S37, the processing is branched off based on the valueof the repeat counter C. That is, the value of the register c isregarded as an integer. Then, if the value is not 1, the value of therepeat counter C is decreased by 1 and the process returns to step S35.Since when the processing enters to the loop, a=d₁, d=d₃ ≈(1/2)d₁^(-1/2), if the value d is repeatedly renewed in step S35 (that is, g(d,a)→d), the value d approaches to (1/2)a^(-1/2) =(1/2)d₂ ^(-1/2).

Since when the processing in step S35 is iterated for R times, C=1, theprocessing gets out of the aforementioned loop. The value d at this timeis determined as d₆.

If the number of occurrence R is selected so that an error |d₆ -(1/2)d₁^(1/2) | at the completion of iteration is less than the numericprecision of the DSP, the value d₆ can be regarded as a true value of(1/2)d₁ ^(-1/2). Therefore, the value d₆ of the register d at thecompletion of the processing in FIG. 9 is as the following:

    d.sub.6 =(1/2)d.sub.1.sup.-1/2 =(1/2) q.sub.2 (n).sup.-1/2 (74)

Therefore, it is understood that the processing in the operationapparatus 34 in FIG. 5 is realized by the processing shown in theflowchart in FIG. 9.

Third Embodiment

The third embodiment according to the present invention is described.

FIG. 10 is a block diagram illustrating the structure of a digitalautomatic gain controller (which is referred to as a "controller")according to the third embodiment of the present invention. Thecontroller is comprised of the full-wave rectifier 311 which obtains anabsolute value of a signal, low pass filters (LPFs) 312 and 110 whichaverage a signal, operation apparatuses 112 and 314 which calculate(1/2)x^(-1/2) for 1/2≦x≦1, multipliers 315 and 319, multipliers 114 and317, and constant multipliers 318, 111, 113, 115, and 116. V₀ is apredetermined effective value.

Furthermore, r₃ (n), r₃₁ (n), r₃₂ (n), r₃₃ (n), r₃ '(n), v₃ (n), u₃ (n),t₃ (n), g₁ (n), K'(n), P_(i3) (n), q₃ (n), and g₂ (n) are signal valuesat each portion of the controller at the sampling time n. Among those,K'(n) is an integer and the other values are decimals in which absolutevalues are less than 1. The processing in the present controller iscomprised of the software of the fixed point DSP. FIG. 11 illustrates afixed point format of the DSP. The "S", black dot, "N" respectivelyrepresent a sign bit, a decimal, and the total bit.

As shown in FIG. 10, the structure of the AGC in the present controlleris that the two-stage feed forward type AGC is successively connectedThe first stage is a part to obtain the amplification signal r₃₂ (n)from the input signal r₃ (n). The second step is a part to obtain theamplification output signal r₃ '(n) from the amplification signal r₃₂(n).

In the first stage AGC, the signal is roughly amplified, and in thesecond stage AGC, the signal is corrected so that the effective value ofthe output signal r₃ '(n) is to be the predetermined value v₀.

First of all, the absolute value of the input signal r₃ (n) is obtainedby the full-wave rectifier 311 and averaged by the LPF 312. The meanamplification v₃ (n) of the input signal r₃ (n) is obtained as thefollowing:

    v.sub.3 (n)=E|r.sub.3 (n)|               (75)

Then, in the multiplier 313, the following equation is calculated:

    K'(n)=-[log.sub.2 v.sub.3 (n)]                             (76)

At the same time, the mean amplitude v₃ (n) is multiplied by2^(K')(n)-1, and the normalized amplitude u₃ (n) is obtained. However,[x] represents a maximum integer which is less than x. The multiplier313 outputs u₃ (n) and K'(n) to the operation apparatus 314 andmultiplier 16 respectively.

From the above equation (76), u₃ (n) is obtained as the following:##EQU23## Then, the following relation is formed:

    -1≦log.sub.2 v.sub.3 (n)-[log.sub.2 v.sub.3 (n)]-1<0 (78)

Therefore, the normalized amplitude u₃ (n) satisfies the followingcondition:

    2.sup.-1 ≦u.sub.3 (n)<1                             (79)

In the operation apparatus 314, the following equation is calculated:

    t.sub.3 (n)=(1/2)u.sub.3 (n).sup.-1/2                      (80)

Furthermore, t₃ (n) is squared by the multiplier 315 and theamplification gain g₁ (n) is obtained by: ##EQU24##

Furthermore, the value r₃₁ (n) is obtained in a manner such that theinput signal r₃ is multiplied by 2^(n) in the multiplier 16 based onK'(n) which is inputted from the multiplier 313. That is:

    r.sub.31 (n)=r.sub.3 (n)×2.sup.k'(n)-3               (82)

If r₃₁ (n) is multiplied by the amplification gain g₁ (n) by themultiplier 317, and the product is then multiplied by 4, anamplification signal r₃₂ (n) can be obtained by using the equation (81)by: ##EQU25## That is, the equivalent divider is comprised of thecombination of the operation apparatus 314, multiplier 315, multiplier317, and constant multiplier 318.

If the equations (77) and (82) are substituted in the above equation(83), the following equation is obtained: ##EQU26##

If the mean amplitude v₃ (n) is a certain value, the effective value ofthe amplification signal r₃₂ (n) which is an output of the first stageAGC can be obtained from the equation (84): ##EQU27## Suppose that theproportion of the effective value of the input signal r₃ (n) (asquare-root of Er₃ (n)²) to the mean amplitude v₃ (n)=E|r₃ (n)| of thevalue r₃ is as the following: ##EQU28## Then, the equation (85) becomesas the following: ##EQU29## However, the range of α is the empiricalvalue. That is, the first stage AGC is operated so that the effectivevalue of the amplification signal r₃₂ (n) is one-fourth of theproportion of the effective value of the input signal r₃ (n) to the meanamplitude. Furthermore, from the equations (86) and (87), the followingrelation is formed: ##EQU30## Since the peak values of r₃ (n), r₃₁ (n),r₃₂ (n), r₃₃ (n), and r₃ '(n) are empirically known that they aresmaller than the tripled effective values of r₃ (n), r₃₁ (n), r₃₂ (n),r₃₃ (n), and r₃ '(n), it is apparent that the following relation isformed: ##EQU31## That is, the amplification signal r₃₂ (n) is amplifiedso as not to overflow in the fixed point format shown in FIG. 11.

The effective value of the output signal r₃₂ (n) of the first stage AGCis α/4 as indicated in the equation (87). In the second stage AGC, theeffective value of the output signal r₃ '(n) is corrected to be thepredetermined value V₀.

First, the amplification signal r₃₂ (n) is squared by the multiplier 319and averaged by the LPF 110. The mean power P_(i3) (n) of theamplification signal r₃₂ (n) can be obtained by:

    i P.sub.i3 (n)=Er.sub.32 (n).sup.2                         (90)

Then, the mean power P_(i3) (n) is multiplied by 8 by the constantmultiplier 111 and the normalized power q₃ is obtained. When theequations (87) and (90) are used, the the normalized power q₃ isobtained by: ##EQU32## From the equation (86), the normalized power q₃satisfies the following relation:

    2.sup.-1 ≦q.sub.3 (n)<1/2·(4/3).sup.2 =8/9<1 (92)

Then, the correction gain g₂ (n) is calculated by the operationapparatus 112 from the normalized power q₃ (n) as the following:

    g.sub.2 (n)=(1/2) q.sub.3 (n).sup.-1/2                     (93)

On the other hand, the amplification signal r₃₂ (n) is multiplied by1/√2 by the constant multiplier 113, and the value r₃₃ (n) is obtained.Furthermore, the value r₃₃ (n) is multiplied by the correction gain g₂(n) by the multiplier 114, and further multiplied by the predeterminedeffective value v₀ and 8 by the constant multipliers 115 and 116respectively. Then, the output signal r₃ '(n) is obtained by: ##EQU33##When the equations (90), (91), (93), and (94) are used, r₃ '(n) isobtained by: ##EQU34##

That is, the second stage AGC has the function that the amplificationsignal r₃₂ (n) is divided by the effective value (the square root of themean power) and multiplied by the predetermined effective value.

If the effective value of the output signal r₃ '(n) of the second stageAGC is obtained, from the equation (96), the following is obtained:##EQU35## It is obvious that the output signal r₃ '(n) is equal to thepredetermined effective value v₀ from the above equation.

The internal signal processing in the multiplier 313 is described belowalong with FIG. 12. As shown in the diagram, the multiplier 313 iscomprised of the constant subtracters 411, 421, 431, 441, the operationapparatuses 412, 413, 422, 423, 432, 433, 442, 443 which select anoutput value according to the sign of an inputted signal, themultipliers 414, 424, 434, 444, and the adder 425, 435, 445.Furthermore, V_(k) (n) and I_(k) (n) (k=1, 2, 3, 4) are signal values ateach portion of the multiplier at the sampling time n. The value V_(k)(n) is a decimal in which the absolute value is less than 1, and I_(k)(n) is an integer. The case where the mean amplitude v₃ (n) which wasinputted into the multiplier 13 satisfies the following condition is nowto be described:

    2.sup.-15 ≦v.sub.3 (n)<1                            (98)

First, 2⁻⁸ is subtracted from the inputted mean amplitude v₃ (n) by theconstant subtracter 411. The result of v₃ (n)-2⁻⁸ is outputted to theoperation apparatuses 412 and 413. Then, in the operation apparatuses412 and 413, the following equations are calculated based on the sign ofthe result of v₃ (n)-2⁻⁸ :

    I.sub.1 (n)=8·max(0, -sgn(v.sub.3 (n)-2.sup.-8))  (99)

    v.sub.31 (n)/v.sub.3 (n)=max(1, -2.sup.-8 ·sgn(v.sub.3 (n) -2.sup.-8))                                               (100)

The results are outputted to the multiplier 414 and adder 425. However,to an arbitrary real number, the following condition is satisfied:##EQU36## It should be noted that max(x, y) represents the value x or ywhich is greater than the other. From the equation (100), the followingis obtained: ##EQU37## The output v₃₁ (n)/v₃ (n) of the operationapparatus 413 is multiplied by v₃ (n) by the multiplier 414, and thefollowing is obtained: ##EQU38## It is obvious that v₃₁ (n) satisfiesthe following condition:

    2.sup.-8 ≦v.sub.31 (n)<1                            (104)

Furthermore, a logarithm of the both sides of the equation (102) is asthe following: ##EQU39## In the summary:

    2.sup.-8 ≦v.sub.31 (n)<1                            (106)

    log.sub.2 v.sub.31 (n)-log.sub.2 v.sub.3 (n)=I.sub.1 (n)   (107)

Similarly, from FIG. 12, the following relations are formed:

    2.sup.-4 ≦v.sub.32 (n)<1                            (108)

    log.sub.2 v.sub.32 (n)-log.sub.2 v.sub.31 (n)=I.sub.2 (n)-I.sub.1 (n) (109)

    2.sup.-2 ≦v.sub.33 (n)<1                            (110)

    log.sub.2 v.sub.33 (n)-log.sub.2 v.sub.32 (n)=I.sub.3 (n)-I.sub.2 (n) (111)

    2.sup.-1 ≦u.sub.3 (n)<1                             (112)

and

    log.sub.2 u.sub.3 (n)-log.sub.2 v.sub.33 (n)=I.sub.4 (n)-I.sub.3 (n) (113)

If the terms of the equations (105), (109), (111), and (113) arerespectively added in each side, the following is obtained:

    log.sub.2 u.sub.3 (n)-log.sub.2 v.sub.33 (n)=I.sub.4 (n)   (114)

Finally, 1 is added to I₄ (n) by the adder 445 and K'(n) is obtained. Ifthe equation (114) is used:

    K'(n)=I.sub.4 (n)+1=log.sub.2 u.sub.3 (n)-log.sub.2 v.sub.33 (n)+1 ∴ log.sub.2 v.sub.33 (n)=log.sub.2 u.sub.3 (n)-K'(n)+1 (115)

From the equation (112), the following relation is formed:

    -1≦log.sub.2 u.sub.3 (n)<0                          (116)

Therefore, the following relations are obtained:

    -1+(-K'(n)+1)≦log.sub.2 u.sub.3 (n)+(-K'(n)+1)<-K'(n)+1 ∴-K'(n)≦log.sub.2 u.sub.3 (n)-K'(n)+1<-K'(n)+1 (117)

If the equation (115) is substituted, the following is obtained:

    -K'(n)≦log.sub.2 v.sub.3 (n)<-K'(n)+1               (118)

That is, since -K'(n) is a maximum integer which is not larger than log₂v₃ (n), it can be expressed as the following:

    -K'(n)=[log.sub.2 v.sub.3 (n)]                             (119)

Therefore, K'(n) and v₃ (n) in FIG. 12 satisfy the equation (76) whichdefines K'(n) and v₃ (n).

Furthermore, from the equation (115) the following relation is formed:##EQU40## Therefore, it is indicated that u₃ (n) in FIG. 12 satisfiesthe equation (77).

As described above, u₃ (n) and K'(n) which are obtained in the signalprocessing apparatus shown in FIG. 12 satisfy the definition equationsfor u₃ (n) and K'(n) which are the outputs of the multiplier 13 in FIG.10.

Furthermore, since the internal processing in the operation apparatuses314 and 112 in the controller shown in FIG. 10 is the same as that inthe operation apparatus 34 in the second embodiment shown in FIG. 5, thedescription is omitted here.

As described above, according to the third embodiment, in the digitalautomatic gain controller having the two-stage feed forward type AGC, itis corrected so that the effective value of the output signal is equaledto the predetermined value in the second stage AGC without using afeedback loop in a manner such that the effective value of the firststage AGC is amplified to be approximately 1/4 of the original value inthe first stage AGC when an equivalent division is performed in the bothAGCs. In this way, the effective value of the output signal can beequaled to the predetermined value without using the feedback loop.Furthermore, in the contract to the the feedback type AGC, an optimalgain control at the current time can be performed in a manner such thata gain is successively corrected, not converged.

Therefore, principally, the initial response becomes quick and the gaincan be converged before the PN segment regardless of the receptionsignal level.

Furthermore, in the third embodiment, the case where the input v₃ (n) tothe multiplier 13 is over 2⁻¹⁵ has been described. However, more subtlesignal can be processed in a manner such that the controller shown inFIG. 12 is developed in the same structure.

The present invention is not limited to the above described first tothird embodiment. Various changes and modifications may be made in theinvention without departing from the spirit and scope thereof. Forexample, in the internal processing in the operation apparatus, theorder of the operations on the mantissa and exponent can be switched andthe application using the register and memory can be also modified.

Furthermore, it goes without saying that the structure of the AGC is notcomprised of the DSP, but of a general purpose microprocessor.

The present invention can be applied to a system constituted by aplurality of devices, or to an apparatus comprising a single device.Furthermore, it goes without saying that the invention is applicablealso to a case where the object of the invention is attained bysupplying a program to a system or apparatus.

As many apparently widely different embodiments of the present inventioncan be made without departing from the spirit and scope thereof, it isto be understood that the invention is not limited to the specificembodiments thereof except as defined in the appended claims.

What is claimed is:
 1. A digital gain controller comprising: operationmeans for calculating a mean power of an input signal;first signalgeneration means for generating a normalized power signal by multiplyingthe mean power by 2^(N) (N is an integer), said normalized power signalhaving a value in the range of 1/2 to 1; second signal generation meansfor generating a gain correction signal based on the normalized powersignal; third signal generation means for generating an amplificationsignal by multiplying the input signal by 2.sup.(N/2)-2 (N is aninteger); and fourth signal generation means for generating an outputsignal by multiplying the amplification signal by both the gaincorrection signal and a predetermined constant.
 2. A digital gaincontroller comprising:operation means for calculating a mean amplitudeof an input signal; first gain controller for generating anamplification signal which is proportional to the input signal, saidamplification signal having an effective value equal to one-fourth ofthe ratio of an effective value of the input signal to the meanamplitude; and second gain controller for generating an output signalwhich is proportional to the amplification signal, said output signalhaving an effective value which is equal to the predetermined effectivevalue of said amplification signal; wherein said first gain controllerfurther comprises: means for obtaining a normalized amplitude having thevalue in the range of 1/2 to 1 which is obtained by multiplying a meanamplitude by 2^(N) (N is an integer); means for multiplying an inputsignal by 2^(N-2) (N is an integer); and means for equivalently dividingthe input signal which was multiplied by 2^(N-2) by the normalizedamplitude.
 3. A gain control method comprising the steps of:(a)calculating a mean power of an input signal; (b) generating a normalizedpower signal having the value in the range of 1/2 to 1 by multiplyingthe mean power by 2^(N) (N is an integer); (c) generating a gaincorrection signal based on said normalized power signal by multiplyingthe inverse square-root of the normalized power signal by 1/2; (d)generating an amplification signal by multiplying the input signal by2.sup.(N/2)-2 (N is an integer); and (e) generating an output signal bymultiplying the amplification signal by the gain correction signal and apredetermined constant.
 4. A digital gain controllercomprising:operation means for calculating a mean power of an inputsignal; first signal generation means for generating a normalized powersignal by multiplying the mean power by 2^(N) (N is an integer), saidnormalized power signal having a value in the range of 1/2 to 1; secondsignal generation means for generating a gain correction signal based onthe normalized power signal, said gain correction signal being equal tothe inverse square root of the normalized power signal multiplied by1/2; third signal generation means for generating an amplificationsignal by multiplying the input signal by 2.sup.(N/2)-2 (N is aninteger); and fourth signal generation means for generating an outputsignal by multiplying the amplification signal by both the gaincorrection signal and a predetermined constant.
 5. A digital gaincontroller comprising:operation means for calculating a mean amplitudeof an input signal; first gain controller for generating anamplification signal which is proportional to the input signal, saidamplification signal having an effective value equal to one-fourth ofthe ratio of an effective value of the input signal to the meanamplitude; and second gain controller for generating an output signalwhich is proportional to the amplification signal, said output signalhaving an effective value which is equal to the predetermined effectivevalue of said amplification signal; wherein said second gain controllerfurther comprises; means for calculating a mean power of anamplification signal; and means for equivalently dividing theamplification signal by the inverse square-root of the mean power andmultiplying by the predetermined effective value.
 6. A gain controllercomprising:first converting means for converting a mean power of aninput signal into a normalized power signal; second converting means forconverting the normalized power signal into a gain correction signal;third converting means for converting the input signal into anamplification signal in accordance with a normalizing process performedby said first converting means; and fourth converting means forconverting the amplification signal into a gain controlled output signalin accordance with the gain correction signal, wherein the normalizedpower signal has a value in the range which is determined by aconverting process performed by said second converting means.
 7. Thecontroller according to claim 6, wherein the range which is determinedby said second converting means is from 1/2 to
 1. 8. The controlleraccording to claim 6, wherein the amplification signal is proportionalto a ratio between the mean power and the normalized power signal. 9.The controller according to claim 6, wherein the gain correction signalis proportional to an inverse square-root of the normalized powersignal.
 10. The controller according to claim 6, wherein said fourthconverting means converts the amplification signal into the gaincontrolled output signal having a value equal to a predeterminedeffective value.
 11. A gain control method comprising:a first convertingstep of converting a mean power of an input signal into a normalizedpower signal; a second converting step of converting the normalizedpower signal into a gain correction signal; a third converting step ofconverting the input signal into an amplification signal in accordancewith a normalizing process performed in said first converting step; anda fourth converting step of converting the amplification signal into again controlled output signal in accordance with the gain correctionsignal, wherein the normalized power signal having a value in a rangewhich is determined by a converting process performed in said secondconverting step.
 12. The method according to claim 11, wherein the rangewhich is determined by the converting process performed in said secondconverting step is from 1/2 to
 1. 13. The method according to claim 11,wherein the amplification signal is proportional to the input signal anda ratio between the mean power and the normalized power signal.
 14. Themethod according to claim 11, wherein the gain correction signal isproportional to an inverse square-root of the normalized power signal.15. The method according to claim 11, wherein in said fourth convertingstep, the amplification signal is converted into the gain controlledoutput signal having a value equal to a predetermined effective value.16. A gain controller comprising:a first gain controller for convertingan input signal into an intermediate signal based on a mean amplitude ofthe input signal; and a second gain controller for converting theintermediate signal into a gain controlled output signal based on a meanpower of the intermediate signal, wherein said first gain controllerincludes first converting means for converting the mean amplitude of theinput signal into a normalized amplitude signal, second converting meansfor converting the normalized amplitude signal into a gain correctionsignal, third converting means for converting the input signal intoamplification signal, and fourth converting means for converting theamplification signal into the intermediate signal in accordance with thegain correction signal.
 17. The controller according to claim 16,wherein the normalized amplitude signal has a value in a range which isdetermined by a converting process performed by said second convertingmeans.
 18. The controller according to claim 17, wherein the range isfrom 1/2 to
 1. 19. The controller according to claim 16, wherein saidthird converting means converts the input signal into the amplificationsignal in accordance with a converting process performed by said secondconverting means.
 20. The controller according to claim 16, wherein theamplification signal is proportional to a ratio between the meanamplitude and the normalized amplitude signal.
 21. The controlleraccording to claim 16, wherein the gain correction signal isproportional to an inverse of the normalized amplitude signal.
 22. Thecontroller according to claim 16, wherein said second gain controllerincludes first power converting means for converting a mean power of theintermediate signal into a normalized power signal, second powerconverting means for converting the normalized power signal into a powergain correction signal, and amplitude converting means for convertingthe intermediate signal into the gain controlled output signal inaccordance with the power gain control signal.
 23. The controlleraccording to claim 22, wherein the normalized power signal has a valuein a range which is determined by a converting process performed by saidsecond power converting means.
 24. The controller according to claim 23,wherein the range is from 1/2 to
 1. 25. The controller according toclaim 22, wherein the power gain correction signal is proportional to aninverse square-root of the normalized power signal.
 26. The controlleraccording to claim 22, wherein said amplitude converting means convertsthe intermediate signal into a gain controlled output signal having avalue equal to a predetermined effective value.
 27. A gain controlmethod comprising:a first gain control step of converting an inputsignal into an intermediate signal based on a mean amplitude of theinput signal; and a second gain control step of converting theintermediate signal into a gain controlled output signal based on a meanpower of the intermediate signal, wherein said first gain control stepincludes a first converting step of converting the mean amplitude of theinput signal into a normalized amplitude signal, a second convertingstep of converting the normalized amplitude signal into a gaincorrection signal, a third converting step of converting the inputsignal into amplification signal, and a fourth converting step ofconverting the amplification signal into the intermediate signal inaccordance with the gain correction signal.
 28. The method according toclaim 27, wherein the normalized amplitude signal has a value in a rangewhich is determined by a converting process performed in said secondconverting step.
 29. The method according to claim 28, wherein the rangeis from 1/2 to
 1. 30. The method according to claim 27, wherein in saidthird converting step, the input signal is converted into theamplification signal in accordance with a converting process performedin said second converting step.
 31. The method according to claim 27,wherein the amplification signal is proportional to a ratio between themean amplitude and the normalized amplitude signal.
 32. The methodaccording to claim 27, wherein the gain correction signal isproportional to an inverse of the normalized amplitude signal.
 33. Themethod according to claim 27, wherein second gain control step includesa first power converting step of converting a mean power of theintermediate signal into a normalized power signal, a second powerconverting step of converting the normalized power signal into a powergain correction signal, and an amplitude converting step of convertingthe intermediate signal into the gain controlled output signal inaccordance with the power gain control signal.
 34. The method accordingto claim 33, wherein the normalized power signal has a value in a rangewhich is determined by a converting process performed in said secondpower converting step.
 35. The method according to claim 34, wherein therange is from 1/2 to
 1. 36. The method according to claim 33, whereinthe power gain correction signal is proportional to an inversesquare-root of the normalized power signal.
 37. The method according toclaim 33, wherein in said amplitude converting step, the intermediatesignal is converted into a gain controlled output signal having a valueequal to a predetermined effective value.
 38. A gain controllercomprising:a first gain controller for converting an input signal intoan intermediate signal based on a mean amplitude of the input signal;and a second gain controller for converting the intermediate signal intoa gain controlled output signal based on a mean power of theintermediate signal, wherein said second gain controller includes firstpower converting means for converting a mean power of the intermediatesignal into a normalized power signal, second power converting means forconverting the normalized power signal into a power gain correctionsignal, and amplitude converting means for converting the intermediatesignal into the gain controlled output signal in accordance with thepower gain correction signal.
 39. The controller according to claim 38,wherein the normalized power signal has a value in a range which isdetermined by a converting process performed by said second powerconverting means.
 40. The controller according to claim 39, wherein therange is from 1/2 to
 1. 41. The controller according to claim 38,wherein the power gain correction signal is proportional to an inversesquare-root of the normalized power signal.
 42. The controller accordingto claim 38, wherein said amplitude converting means converts theintermediate signal into a gain controlled output signal having a valueequal to a predetermined effective value.
 43. A gain control methodcomprising:a first gain control step of converting an input signal intoan intermediate signal based on a mean amplitude of the input signal;and a second gain control step of converting the intermediate signalinto a gain controlled output signal based on a mean power of theintermediate signal; wherein said second gain control step includes afirst power converting step of converting a mean power of theintermediate signal into a normalized power signal, a second powerconverting step of converting the normalized power signal into a powergain correction signal, and an amplitude converting step of convertingthe intermediate signal into the gain controlled output signal inaccordance with the power gain control signal.
 44. The method accordingto claim 43, wherein the normalized power signal has a value in a rangewhich is determined by a converting process performed in said secondpower converting step.
 45. The method according to claim 44, wherein therange is from 1/2 to
 1. 46. The method according to claim 43, whereinthe power gain correction signal is proportional to an inversesquare-root of the normalized power signal.
 47. The method according toclaim 43, wherein in said amplitude converting step, the intermediatesignal is converted into a gain controlled output signal having a valueequal to a predetermined effective value.